This invention relates primarily to a hardware logic simulator for use in carrying out logic simulation of a logic circuit or device which may be an LSI.
Hardware logic simulators are revealed in U.S. patent application Ser. No. 513,489 filed July 13, 1983, by Tohru Sasaki now U.S. Pat. No. 4,725,975, one of the present applicants, and Ser. No. 514,900 filed July 18, 1983, by Kenji Ohmori, now U.S. Pat. No. 4,541,071 both for assignment to the instant assignee. Various other hardware logic simulators are also known. Generally speaking of the prior art hardware logic simulators, an overall logic operation of a logic circuit is simulated by storing results of simulation in memories. The memories must have an enormous memory capacity. For example, the number of memory elements or cells amounts to 2.sup.n when the logic circuit has n inputs.